1. Field of the Invention
The present invention relates to floating-calculation apparatuses and, more particularly to an apparatus for floating-point addition and subtraction using a digital circuit. More specifically, the present invention relates to a structure of a circuit for addition and subtraction of exponent values in order to align fraction parts for floating-point addition and subtraction.
2. Description of the Background Art
FIG. 16 is a diagram showing a structure of a format for floating-point representation. Referring to FIG. 16, a floating-point number has an exponent part storing an exponent value E, a fraction part storing a fraction value (or a mantissa value) F and a sign part storing a sign bit SG representing a sign of the fraction value of the fraction part. The floating-point number is represented by (xe2x88x921)SGxc2x7(1.F)2E+BIAS. Here, xe2x80x9cBIASxe2x80x9d represents a bias value for normalization. The fraction and exponent values are generally represented by the hexadecimal system.
Such floating-point number can accommodate a significant number with a large number of digits, and is widely used for scientific calculation or the like.
For addition or subtraction of such floating-point numbers, digits thereof must be aligned as in the case of a usual addition or subtraction of the decimal numbers. Thus, for floating-point addition or subtraction, a fraction part of a smaller floating-point number is right-shifted (logic right-shifted), so that the exponent values of the floating-point numbers, between which addition or subtraction is performed, can be equalized.
Now, digit alignment of two operands NA and NB will be considered with reference to FIG. 17(A). Operand NA is represented in the floating-point representation using the hexadecimal system, and has a sign bit, exponent value and fraction value of 0, xe2x80x9c43xe2x80x9d and xe2x80x9c65123Axe2x80x9d, respectively. The second operand NB has the sign bit, exponent value and fraction value of xe2x80x9c0xe2x80x9d, xe2x80x9c3Fxe2x80x9d and xe2x80x9cCBA987xe2x80x9d, respectively.
The exponent value xe2x80x9c43xe2x80x9d of first operand NA is greater than the exponent value xe2x80x9c3Fxe2x80x9d of second operand NB. Thus, in order to make the exponent value xe2x80x9c3Fxe2x80x9d of second operand NB equal to the exponent value xe2x80x9c43xe2x80x9d of first operand NA, the fraction part of second operand NB is shifted in a right direction and, the exponent value of second operand NB is increased every time the fraction part is shifted.
First, with reference to FIG. 17(B), the fraction value of second operand NB is right-shifted by 1 bit. In the most significant bit position, xe2x80x9c0xe2x80x9d is inserted. In other words, logic right-shift is performed on the fraction part. As a result of the right-shift by 1 bit, the exponent value of second operand NB is increased by 1 and turns to xe2x80x9c40xe2x80x9d.
Thereafter, as shown in FIG. 17(C), the fraction value of the second operand is further light-shifted by 1 bit, so that the exponent value of the second operand is increased by 1. As the exponent value xe2x80x9c41xe2x80x9d is still smaller than the exponent value xe2x80x9c43xe2x80x9d of first operand NA, right-shifting is further performed as shown in FIGS. 17(D) and 17(E). As shown in FIG. 17(E), the exponent value xe2x80x9c43xe2x80x9d of second operand NA is made equal to the exponent value of first operand NA, and thus digit alignment of the fraction values of first and second operands NA and NB is completed. Subsequently, addition or subtraction of first and second operands NA and NB, respectively shown in FIGS. 17(A) and 17(E), is executed.
Thus, for addition or subtraction of the floating-point numbers, determination must be made as to which of the fraction values of two operands must be right-shifted. To that end, it is necessary to compare the exponent values of two operands, determine the operand (floating-point number) to be right-shifted, and calculate the difference of the exponent values to determine an amount to be right-shifted.
FIG. 18 is a diagram schematically showing a structure of a right-shift amount determination portion in a conventional floating-point calculation apparatus. The structure shown in FIG. 18 is described, for example, in Suzuki et al., xe2x80x9cLeading-Zero Anticipatory Logic for High-Speed Floating Point Additionxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 31, #8, pp. 1157-1164, August 1996.
In FIG. 18, a shift amount calculation portion calculates a shift amount for two floating-point numbers (operands) NA and NB. Floating-point number NA has an exponent value EA and a fraction value FA, whereas floating-point number NB has an exponent value EB and a fraction value FB.
As shown in FIG. 18, the shift amount calculation portion includes two 2""s complement subtractors 701 and 702 arranged in parallel, and a comparator 703 for comparing exponent values EA and EB. 2""s complement subtractor 701 has its inputs IA and IB respectively receiving exponent values EA and EB, and subtracts exponent value EB applied to input IB from exponent value EA applied to input IA. Here, 2""s complement subtractor 701 converts exponent value EB applied to input IB to a 2""s complement for addition, and outputs the addition result from an output O. On the other hand, 2""s complement subtractor 702 subtracts exponent value EA applied to input IB from exponent value EB applied to input IA, and outputs a value indicating the subtraction result from output O.
Comparator 703 asserts a signal output from 0 xe2x80x9c1xe2x80x9d when exponent value EA applied to an input CA thereof is equal to or greater than exponent value EB applied to an input CB thereof. When exponent value EA applied to input CA is smaller than exponent value EB applied to input CB, the signal from output O is asserted xe2x80x9c0xe2x80x9d by comparator 703.
The shift amount calculation portion further includes: a multiplexer 704 having its inputs I1 and I0 respectively receiving output values from 2""s complement subtractors 701 and 702 for selecting one of the output values in accordance with an output signal from comparator 703 for outputting from output O; a multiplexer 705 having its inputs I0 and I1 respectively receiving fraction values FA and FB of floating-point numbers NA and NB for selecting one of the fraction values in accordance with the output signal from comparator 703 and outputting a fraction value FC; and a multiplexer 706 having its inputs I0 and I1 respectively receiving fraction values FB and FA for selecting one of the fraction values in accordance with the output signal from comparator 703 and outputting a fraction value FD from output O. Digit-shifting is performed for fraction value FC from multiplexer 705 by a right-shift circuit (not shown), whereas fraction value FD from multiplexer 706 is not right-shifted and applied to an adder (not shown).
Two 2""s complement subtractors 701 and 702 are used with the following reasons. When a large exponent value is subtracted from a small exponent value, a negative value is produced so that a shift amount cannot be determined correctly. For the determination of the shift amount, an absolute value of the difference must be calculated. The 2""s complement subtractors 701 and 702 are used for absolute value subtraction for calculating the absolute value of the difference. In 2""s complement subtractors 701 and 702, two exponent values EA and EB are applied in reversed arrangements. Thus, one subtractor produces a positive value, and the other produces a negative value. Comparator 703 determines which of the subtractors outputs the negative value. The absolute value of the difference |EAxe2x88x92EB| between exponent values EA and EB determines a right-shift amount of the fraction value. On the other hand, the output signal from comparator 703 also indicates which of the fraction values must be right-shifted, and multiplexers 705 and 706 select the fraction value to be right-shifted and that not to be right-shifted. Now, the operation will briefly be described.
The 2""s complement subtractors 701 and 702 respectively produce values (EAxe2x88x92EB) and (EBxe2x88x92EA). Comparator 703 asserts xe2x80x9c1xe2x80x9d when exponent value EA is equal to or greater than exponent value EB. If the output signal from comparator 703 is xe2x80x9c1xe2x80x9d, multiplexer 704 selects a value of difference (EAxe2x88x92EB) applied to input I1, and otherwise selects a value of difference (EBxe2x88x92EA) applied to input I0. When the output signal from comparator 703 is asserted xe2x80x9c1xe2x80x9d, exponent value EA is equal to or greater than exponent value EB, and the value of difference (EAxe2x88x92EB) is positive or 0. On the other hand, when the output signal from comparator 703 is xe2x80x9c0xe2x80x9d, the value of difference (EBxe2x88x92EA) is positive. In this case, multiplexer 704 selects the value of difference (EBxe2x88x92EA) applied to input I0. Thus, the absolute value of difference |EAxe2x88x92EB| between exponent values EA and EB is output from multiplexer 704.
Multiplexer 705 selects a numerical value applied to one of its inputs in the same manner as multiplexer 704. More specifically, when the output signal from comparator 703 is asserted xe2x80x9c1xe2x80x9d and exponent value EA is equal to or greater than exponent value EB, multiplexer 705 selects fraction value FB applied to input I1, and otherwise multiplexer 705 selects fraction value FA applied to input I0. If the output signal from comparator 703 is asserted xe2x80x9c1xe2x80x9d, floating-point number NA is greater than floating-point number NB, and thus fraction value FB must be right-shifted. On the other hand, if NA is not greater than NB, fraction value FA must be right-shifted. Therefore, multiplexer 705 selects fraction value FC of the floating-point number with a smaller exponent value for application to a right-shift circuit (not shown).
On the other hand, multiplexer 706 receives fraction values FA and FB in reversed arrangement with reference to multiplexer 705, and therefore, a fraction value of the floating-point number with a larger exponent value is selected in multiplexer 706. Thus, fraction value FD from multiplexer 706 is not right-shifted.
As the above described two subtractors and the comparator are used, calculation of the right-shift amount and selection of the fraction value to be right-shifted are simultaneously performed. However, provision of two subtractors disadvantageously increases circuit scale and power consumption. In the floating-point representation, generally, a format of exponent and fraction values are standardized as shown in FIG. 16. A floating-point number generally includes an 1-bit sign, 15-bit exponent and 64-bit significand (63-bit fraction). Thus, subtractors 701 and 702 must perform subtraction of 15-bit exponent values, so that the circuit scale thereof extremely increases and power consumption also increases accordingly.
FIG. 19 is a diagram schematically showing another structure of the conventional right-shift amount calculation portion. As shown in FIG. 19, the right-shift amount calculation portion includes: a 2""s complement subtractor 801 subtracting exponent value EB from exponent value EA; a 2""s complement subtractor 802 subtracting exponent value EA from exponent value EB; and a multiplexer 804 selecting one of output values (EAxe2x88x92EB) and (EBxe2x88x92EA) from 2""s complement subtractors 801 and 802 in accordance with a carryout signal Cout from 2""s complement subtractor 802. 2""s complement subtractor 802 asserts its carryout signal Cout xe2x80x9c1xe2x80x9d when exponent value EB applied to an input IA thereof is greater than or equal to exponent value EA applied to an input IB thereof. Multiplexer 804 selects a value of difference (EBxe2x88x92EA) applied to input I1 when carryout signal Cout applied to a selection input S thereof is xe2x80x9c1xe2x80x9d and otherwise selects the value of difference (EAxe2x88x92EB) applied to input 10. Thus, the absolute value of difference |EAxe2x88x92EB| between exponent values EA and EB is output from multiplexer 804.
The right-shift amount calculation portion further includes: a multiplexer 805 having its inputs I1 and I0 respectively receiving fraction values FA and FB for selecting one of the fraction values in accordance with carryout signal Cout applied to a selection input S thereof; and a multiplexer 806 having its inputs I1 and I0 respectively receiving fraction values FB and FA for selecting one of the fraction values in accordance with carryout signal Cout from 2""s complement subtractor 802. Although multiplexers 805 and 806 select one of the inputs in the same manner, the fraction values applied to their inputs are reversely arranged. Thus, when carryout signal Cout is xe2x80x9c1xe2x80x9d, multiplexers 805 and 806 respectively select fraction values FA and FB applied to their inputs I1. On the other hand, when carryout signal Cout is xe2x80x9c0xe2x80x9d, multiplexers 805 and 806 respectively select fraction values FB and FA applied to their input 10. Fraction value FC from multiplexer 805 is applied to a right-shift circuit. Multiplexer 805 selects the fraction value of a floating-point number with a smaller value for application to the right-shift circuit, whereas multiplexer 86 selects the fraction value of a floating point number with a larger value and produces a fraction value FD which is not to be right-shifted.
In the structure shown in FIG. 19, the fact that the exponent value is an integer without a sign is utilized. Carryout signal Cout indicates if the produced subtraction result is positive or negative, which is utilized to calculate the absolute value of the difference between the exponent values. However, also in the structure shown in FIG. 19, two subtractors are used, thereby increasing the scale of the circuit as well as power consumption and chip real estate.
An object of the present invention is to provide a floating-point calculation apparatus capable of reducing chip real estate and power consumption without any decrease in processing speed.
A specific object of the present invention is to provide a floating-point addition and subtraction apparatus capable of performing exponent value subtraction used in floating-point calculation with reduced power consumption and chip real estate.
In short, the present invention includes: a subtractor for subtraction of exponent values; an inverting circuit for inverting an output value from the subtractor; and a circuit for selecting one of the output values from the subtractor and inverting circuit for producing an absolute value of the difference between the exponent values in accordance with a magnitude relation indication signal indicating which exponent value is larger.
More specifically, a floating-point calculation apparatus according to the present invention includes: a subtractor for subtraction of exponent values of first and second operands; an inverting circuit for inverting an output value from the subtractor; and a first selection circuit for selecting one of output values from the subtractor and inverting circuit to produce an absolute value of the difference for right-shifting a fraction value.
Only one subtractor is used for calculating an absolute value of the difference between exponent values, and the inverting circuit only inverts each bit of the output value. The scale of the inverting circuit is sufficiently small as compared with the subtractor, so that reduction in scale of the circuit and power consumption can be achieved. In addition, even when a comparator is used, the scale of the comparator is small as compared with that of the subtractor, so that reduction in chip real estate and power consumption can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.